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ARM: SIMD optimization for 4:4:4:4 to 8:8:8:8 normal blits
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@ -950,6 +950,21 @@ Blit_BGR888_RGB888ARMSIMD(SDL_BlitInfo * info)
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Blit_BGR888_RGB888ARMSIMDAsm(width, height, dstp, dststride, srcp, srcstride);
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}
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void Blit_RGB444_RGB888ARMSIMDAsm(int32_t w, int32_t h, uint32_t *dst, int32_t dst_stride, uint16_t *src, int32_t src_stride);
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static void
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Blit_RGB444_RGB888ARMSIMD(SDL_BlitInfo * info)
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{
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int32_t width = info->dst_w;
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int32_t height = info->dst_h;
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uint32_t *dstp = (uint32_t *)info->dst;
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int32_t dststride = width + (info->dst_skip >> 2);
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uint16_t *srcp = (uint16_t *)info->src;
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int32_t srcstride = width + (info->src_skip >> 1);
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Blit_RGB444_RGB888ARMSIMDAsm(width, height, dstp, dststride, srcp, srcstride);
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}
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#endif
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/* This is now endian dependent */
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@ -3226,6 +3241,10 @@ static const struct blit_table normal_blit_2[] = {
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BLIT_FEATURE_HAS_ALTIVEC, Blit_RGB565_32Altivec, NO_ALPHA | COPY_ALPHA | SET_ALPHA},
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{0x00007C00, 0x000003E0, 0x0000001F, 4, 0x00000000, 0x00000000, 0x00000000,
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BLIT_FEATURE_HAS_ALTIVEC, Blit_RGB555_32Altivec, NO_ALPHA | COPY_ALPHA | SET_ALPHA},
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#endif
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#if SDL_ARM_SIMD_BLITTERS
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{0x00000F00, 0x000000F0, 0x0000000F, 4, 0x00FF0000, 0x0000FF00, 0x000000FF,
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BLIT_FEATURE_HAS_ARM_SIMD, Blit_RGB444_RGB888ARMSIMD, NO_ALPHA | COPY_ALPHA},
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#endif
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{0x0000F800, 0x000007E0, 0x0000001F, 4, 0x00FF0000, 0x0000FF00, 0x000000FF,
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0, Blit_RGB565_ARGB8888, NO_ALPHA | COPY_ALPHA | SET_ALPHA},
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@ -473,3 +473,60 @@ generate_composite_function \
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nop_macro, /* cleanup */ \
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BGR888toRGB888_process_head, \
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BGR888toRGB888_process_tail
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/******************************************************************************/
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.macro RGB444toRGB888_init
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ldr MASK, =0x0f0f0f0f
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/* Set GE[3:0] to 0101 so SEL instructions do what we want */
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msr CPSR_s, #0x50000
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.endm
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.macro RGB444toRGB888_1pixel reg, mask, tmp
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pkhbt WK®, WK®, WK®, lsl #12 @ 0000aaaarrrrggggaaaarrrrggggbbbb
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and WK®, mask, WK® @ 0000aaaa0000gggg0000rrrr0000bbbb
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orr WK®, WK®, WK®, lsl #4 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb
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pkhtb tmp, WK®, WK®, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr
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pkhbt WK®, WK®, WK®, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb
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sel WK®, WK®, tmp @ aaaaaaaarrrrrrrrggggggggbbbbbbbb
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.endm
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.macro RGB444toRGB888_2pixels in, out1, out2, mask, tmp1, tmp2
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and tmp1, mask, WK&in @ 0000RRRR0000BBBB0000rrrr0000bbbb
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and tmp2, mask, WK&in, lsr #4 @ 0000AAAA0000GGGG0000aaaa0000gggg
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orr tmp1, tmp1, tmp1, lsl #4 @ RRRRRRRRBBBBBBBBrrrrrrrrbbbbbbbb
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orr tmp2, tmp2, tmp2, lsl #4 @ AAAAAAAAGGGGGGGGaaaaaaaagggggggg
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pkhtb WK&out2, tmp2, tmp1, asr #16 @ AAAAAAAAGGGGGGGGRRRRRRRRBBBBBBBB
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pkhbt WK&out1, tmp1, tmp2, lsl #16 @ aaaaaaaaggggggggrrrrrrrrbbbbbbbb
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pkhtb tmp2, WK&out2, WK&out2, asr #8 @ AAAAAAAAGGGGGGGGGGGGGGGGRRRRRRRR
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pkhtb tmp1, WK&out1, WK&out1, asr #8 @ aaaaaaaaggggggggggggggggrrrrrrrr
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pkhbt WK&out1, WK&out1, WK&out1, lsl #8 @ ggggggggrrrrrrrrrrrrrrrrbbbbbbbb
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pkhbt WK&out2, WK&out2, WK&out2, lsl #8 @ GGGGGGGGRRRRRRRRRRRRRRRRBBBBBBBB
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sel WK&out1, WK&out1, tmp1 @ aaaaaaaarrrrrrrrggggggggbbbbbbbb
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sel WK&out2, WK&out2, tmp2 @ AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
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.endm
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.macro RGB444toRGB888_process_head cond, numbytes, firstreg, unaligned_src, unaligned_mask, preload
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pixld cond, numbytes/2, firstreg, SRC, unaligned_src
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.endm
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.macro RGB444toRGB888_process_tail cond, numbytes, firstreg
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.if numbytes >= 8
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.if numbytes == 16
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RGB444toRGB888_2pixels %(firstreg+1), %(firstreg+2), %(firstreg+3), MASK, STRIDE_M, SCRATCH
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.endif
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RGB444toRGB888_2pixels %(firstreg+0), %(firstreg+0), %(firstreg+1), MASK, STRIDE_M, SCRATCH
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.else @ numbytes == 4
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RGB444toRGB888_1pixel %(firstreg+0), MASK, SCRATCH
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.endif
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.endm
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generate_composite_function \
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Blit_RGB444_RGB888ARMSIMDAsm, 16, 0, 32, \
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FLAG_DST_WRITEONLY | FLAG_BRANCH_OVER, \
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2, /* prefetch distance */ \
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RGB444toRGB888_init, \
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nop_macro, /* newline */ \
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nop_macro, /* cleanup */ \
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RGB444toRGB888_process_head, \
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RGB444toRGB888_process_tail
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