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Fixed bug 5418 - Add system features detection for Elbrus (E2K)

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Ivan Kuzmenko

MCST Elbrus 2000 (E2K, https://en.wikipedia.org/wiki/Elbrus_2000) is a russian processor architecture based on VLIW/EPIC instruction set (like Intel Itanium (IA-64) architecture). Architecture has half native / half software support of most Intel/AMD SIMD (e.g. MMX/SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AES/AVX/AVX2 & 3DNow!/SSE4a/XOP/FMA4).
It also has built-in x86/x86_64 <-> e2k binary translators  (RTC, http://www.mcst.ru/rtc and Lintel, http://www.mcst.ru/lintel) that can run code for x86/x86_64 architecture (Transmeta did something similiar with their Crusoe series) with SIMD extensions support.
Attached patch allows SDL2 to detect extensions supported by E2K like MMX, 3dNOW!, AVX etc. (test/testplatform log: https://termbin.com/7qs3).
This commit is contained in:
Sam Lantinga 2020-12-28 20:58:47 -08:00
parent 8eae956c98
commit 67f0b9b86d
1 changed files with 95 additions and 0 deletions
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95
src/cpuinfo/SDL_cpuinfo.c
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@ -509,6 +509,17 @@ CPU_haveNEON(void)
#endif
}
#if defined(__e2k__)
inline int
CPU_have3DNow(void)
{
#if defined(__3dNOW__)
return 1;
#else
return 0;
#endif
}
#else
static int
CPU_have3DNow(void)
{
@ -522,7 +533,46 @@ CPU_have3DNow(void)
}
return 0;
}
#endif
#if defined(__e2k__)
#define CPU_haveRDTSC() (0)
#if defined(__MMX__)
#define CPU_haveMMX() (1)
#else
#define CPU_haveMMX() (0)
#endif
#if defined(__SSE__)
#define CPU_haveSSE() (1)
#else
#define CPU_haveSSE() (0)
#endif
#if defined(__SSE2__)
#define CPU_haveSSE2() (1)
#else
#define CPU_haveSSE2() (0)
#endif
#if defined(__SSE3__)
#define CPU_haveSSE3() (1)
#else
#define CPU_haveSSE3() (0)
#endif
#if defined(__SSE4_1__)
#define CPU_haveSSE41() (1)
#else
#define CPU_haveSSE41() (0)
#endif
#if defined(__SSE4_2__)
#define CPU_haveSSE42() (1)
#else
#define CPU_haveSSE42() (0)
#endif
#if defined(__AVX__)
#define CPU_haveAVX() (1)
#else
#define CPU_haveAVX() (0)
#endif
#else
#define CPU_haveRDTSC() (CPU_CPUIDFeatures[3] & 0x00000010)
#define CPU_haveMMX() (CPU_CPUIDFeatures[3] & 0x00800000)
#define CPU_haveSSE() (CPU_CPUIDFeatures[3] & 0x02000000)
@ -531,7 +581,19 @@ CPU_have3DNow(void)
#define CPU_haveSSE41() (CPU_CPUIDFeatures[2] & 0x00080000)
#define CPU_haveSSE42() (CPU_CPUIDFeatures[2] & 0x00100000)
#define CPU_haveAVX() (CPU_OSSavesYMM && (CPU_CPUIDFeatures[2] & 0x10000000))
#endif
#if defined(__e2k__)
inline int
CPU_haveAVX2(void)
{
#if defined(__AVX2__)
return 1;
#else
return 0;
#endif
}
#else
static int
CPU_haveAVX2(void)
{
@ -543,7 +605,15 @@ CPU_haveAVX2(void)
}
return 0;
}
#endif
#if defined(__e2k__)
inline int
CPU_haveAVX512F(void)
{
return 0;
}
#else
static int
CPU_haveAVX512F(void)
{
@ -555,6 +625,7 @@ CPU_haveAVX512F(void)
}
return 0;
}
#endif
static int SDL_CPUCount = 0;
@ -596,6 +667,17 @@ SDL_GetCPUCount(void)
return SDL_CPUCount;
}
#if defined(__e2k__)
inline const char *
SDL_GetCPUType(void)
{
static char SDL_CPUType[13];
SDL_strlcpy(SDL_CPUType, "E2K MACHINE", sizeof(SDL_CPUType));
return SDL_CPUType;
}
#else
/* Oh, such a sweet sweet trick, just not very useful. :) */
static const char *
SDL_GetCPUType(void)
@ -631,9 +713,21 @@ SDL_GetCPUType(void)
}
return SDL_CPUType;
}
#endif
#ifdef TEST_MAIN /* !!! FIXME: only used for test at the moment. */
#if defined(__e2k__)
inline const char *
SDL_GetCPUName(void)
{
static char SDL_CPUName[48];
SDL_strlcpy(SDL_CPUName, __builtin_cpu_name(), sizeof(SDL_CPUName));
return SDL_CPUName;
}
#else
static const char *
SDL_GetCPUName(void)
{
@ -707,6 +801,7 @@ SDL_GetCPUName(void)
return SDL_CPUName;
}
#endif
#endif
int
SDL_GetCPUCacheLineSize(void)